Department of Computer Science
Researcher:
Dr. Cho-Li Wang, Associate Professor (clwang@cs.hku.hk)
Project Title:
Adaptive Mechanisms in Software Transactional Memory
Project Description:
We are now in the era of multicore programming. The old lock-based programming model is being outdated for its increasing difficulty of debugging and limited scalability when there are more threads and processor cores to scale. Software transactional memory (STM) enhances both ease-of-use and concurrency, and is considered one of the next-generation parallel programming paradigms. It is an optimistic programming approach in which threads are put into speculative concurrent executions. The system detects conflicts and allows non-conflicting transactions to commit in parallel. However, application programs may contain hotspots where the system would see intensive conflicts, which would severely degrade the performance. In this situation temporarily stalling some threads could improve the system throughput. There are a few existing concurrency control mechanisms but they are not so effective. One of the reasons is that they observe commit ratio instead commit rate or throughput and can be misled to give a tight bound on the active thread count in some of the programs. For another reason, STM systems are often so rigid that they follow the same protocol for conflict detection for all programs.
Project Significance:
We invent a technique called Probe to control transactional concurrency while monitoring changes in the system throughput. Probe can react swiftly to throughput changes since it makes use of multicore processor cache for low-latency sharing and synchronization of the throughput metadata. We also develop another technique named Select that switches between several compatible concurrency control protocols to accelerate the turnaround time of individual tasks atop the STM. It uses commit ratio to estimate whether a task is more likely to commit or conflict. Correct estimations make the tasks being completed or retried earlier. In future we may investigate accelerating STM with general purpose graphics processing units (GP-GPUs) and porting transactional memory to cluster of multicore computers.
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